Due to recent advances in the field, modern semiconductor integrated circuits have the capability of providing a high degree of functionality and performance with low active power dissipation. In particular, complementary metal-oxide-semiconductor (CMOS) technology provides circuits that can have quite fast switching times with extremely low levels of DC power dissipation. These advances have enabled complex electronic systems to now use batteries and other alternative power sources as primary or backup power. Examples of such systems include portable personal computers of the "notebook" or "laptop" class, personal digital assistants (PDAs), and cellular telephones and facsimile machines.
While many digital circuit functions are readily implemented in CMOS in such a manner that the steady-state power dissipation is extremely low (e.g., CMOS inverters and other logic gates), certain necessary circuit functions are not so easily implemented in that manner. An example of such a circuit function is a clock generator circuit, such as those based on a crystal oscillator. Clock generator circuits are inherently in a constant switching mode, and seldom in a DC state, and thus cannot readily take advantage of the extremely low steady-state power dissipation provided by CMOS technology.
Referring now to FIG. 1, clock generator circuit 10 according to the prior art will now be described in detail. Clock generator circuit 10 utilizes crystal oscillator 14 to generate a periodic signal that is amplified by level shift circuit 16. The amplified periodic signal is then presented to frequency divider 18 to produce an output clock signal of the desired frequency at terminal CLK. According to this conventional approach, reference voltages V.sub.pref and V.sub.nref are generated by low-current reference circuit 12 and applied to crystal oscillator 14 to control the voltage swing of the output clock signal. Reference circuit 12 is preferably configured to include a current source operating in the subthreshold region, as is known in the art (and as will be described hereinbelow), such that the steady-state current dissipated by reference circuit 12 is on the order of 40 nA.
Crystal oscillator 14 is a current-based oscillator of conventional construction, and includes a single gain stage with crystal and resistive feedback. Crystal resonator 15 is a conventional quartz crystal, and is connected off-chip to nodes XTAL1, XTAL2 in the conventional manner. Crystal oscillator 14 includes bias feedback resistor R connected across nodes XTAL1, XTAL2, and crystal frequency control capacitors C.sub.1, C.sub.2 connected between nodes XTAL1, XTAL2, respectively, and ground. The single gain stage in crystal oscillator 14 is provided in the conventional manner by a series of MOS transistors 11, 13, 19. P-channel transistor 11 has its source-drain path connected between V.sub.cc and node XTAL1, and has its gate biased by reference voltage V.sub.pref, N-channel transistor 19 has its source connected to ground and its drain connected to the source of n-channel gain transistor 13; the gate of n-channel transistor 19 is biased by reference voltage V.sub.nref. N-channel gain transistor 13 has its drain connected to node XTAL1 and its gate connected to node XTAL2.
According to this arrangement, transistor 11 operates as a current source load, biased by reference voltage V.sub.pref. Transistor 13 operates as a current-starved inverter, as the current therethrough is limited by transistors 11, 19. As a result, gain transistor 13 is self-biased in the weak inversion regions via resistor R and the current source transistors 11, 19. This current-limited self-biased implementation allows crystal oscillator 14 to operate as a class A or class AB oscillator, preventing significant bias point shift between its DC and AC operating points. In addition, the small signal operation of crystal oscillator 14 ensures low signal and low loss operation of crystal resonator 15.
According to this conventional construction, the output of crystal oscillator 14 is applied to level shift circuit 16, under the same bias conditions, to amplify the small signal output of oscillator 14 prior to application of the signal to frequency divider 18. According to this conventional approach, level shift circuit 16 includes a series of MOS transistors 21, 22, 23 having their source-drain paths connected in series between V.sub.cc and ground. P-channel transistor 21 and n-channel transistor 23 have their gates biased by reference voltages V.sub.pref, V.sub.nref, respectively. N-channel gain transistor 22 has its source connected to the drain of transistor 23, its drain connected to the drain of transistor 21 at node OUT, and its gate connected to oscillator node XTAL2. The signal at node OUT will thus be an amplified version of the oscillator output, and at the same frequency.
Frequency divider 18, according to this conventional arrangement, divides down the amplified signal at node OUT to the desired frequency to produce a clock signal at node CLK for distribution elsewhere in the integrated circuit or the electronic system. Frequency divider 18 is conventionally implemented as a series of counter stages, as is well known in the art, with the appropriate feedback stages implemented as necessary to provide the proper output frequency at node CLK.
According to this conventional approach for generating clock signals, however, the first several counter stages of frequency divider 18 draws significant current, due to the necessity of applying full digital signals to conventional frequency divider counter stages, as produced by level shift circuit 16. The first counter stages of frequency divider 18 are thus switching over large signal swings at relatively high frequencies, causing the high level of significant power dissipation which is undesirable for battery-powered systems.
It is therefore an object of the present invention to provide a clock generator circuit that has reduced current drain and power dissipation relative to conventional clock generator circuits.
It is a further object of the present invention to provide such a circuit which utilizes clocked current sources to limit the overall current requirements of the circuit.
It is a further object of the present invention to provide such a clock generator circuit that is readily implementable in CMOS technology.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following description in combination with its drawings.